The MBHP_Genesis module provides all the hardware necessary to support one of each YM2612/YM3438 (OPN2) and SN76489/94/96 (PSG) sound chips and interface them to a microcontroller (including one of the MIDIbox core modules). In addition, the circuit and board are designed so that up to four MBHP_Genesis modules may be stacked on top of each other to run up to four sets of sound chips, with simple pin/socket headers connecting the boards and no additional wiring needed.

Features:

• High-speed parallel interface to both sound chips, optimized for CORE_STM32F4 ports J10A and J10B, but compatible with most MCUs; requires no other signal connections to the core
• SN76489/94/96 has data latch with automatic deselection, so the MCU can write to it and then immediately use the bus for other things, rather than having to leave the data on the bus until the chip asserted READY
• YM2612/3438 Test and /IRQ pins, and SN76489/94/96 Ready pin, are readable from the core via the parallel interface
• YM2612/3438 Test pin has selectable direction (with protection), and both Test and /IC pins can be written to from the core via the parallel interface
• Analog buffering, filtering, and mixing onboard, all from same +5V power supply (no bipolar +/-12V supply), with OPN2/PSG mixer/pan/volume potentiometer connections
• Filter cutoff frequency selectable between two options (unfiltered or Mega Drive Model 1 mode), separately selectable for OPN2 channels and PSG channel; selection controlled via parallel interface
• SN76494/96 Audio In pin fully supported, with protection
• Separate oscillators for each sound chip; supports 8-DIP or 5x7mm SMT packages
• All parts DIP/through hole (no SMT) (except for optional SMT oscillator)
• Smallest footprint (cheapest board) possible
• Many components may be left unstuffed if certain features not desired!
  
  

Disadvantages:

• Very dense layout
• Larger board than it would be if all the glue logic was removed, and more wires were used to interface to the core (though certain aspects if 2 or 4 boards were used, e.g. reading Ready signals from the PSGs, would require multiple wires or additional logic)
• Parallel interface is +5V, which may cause issues with CORE_STM32F4 (3.0V) or other MCUs at 3.3V. If using only one MBHP_Genesis module, it might work (pending testing) assuming the core tolerates 5V inputs (as CORE_STM32F4 does). However, for two or more boards, due to fanout, an external level shifter circuit will be required. See MBHP_Genesis_LS.