This module is the combination of a quad comparator "voting system" and memory cell (flip-flop). It can be built in many ways to suit the builder's needs. For example, if the memory cell functions are not required, they can be omitted. Alternatively, the panel presence of the comparators can be greatly reduced if the memory cell is the primary interest.

The comparator "voting" circuits can be used as OR, AND or 2 of 3, 2 of 4, 3 of 4 etc. type gates, depending on construction. Both positive responding and negative responding inputs are available.

Master AND and OR outputs monitor the four voting circuits. AND goes HIGH when the outputs of all four comparators are HIGH. OR goes HIGH when the output of at least one of the four comparators is HIGH.

The outputs of the four comparators are used to drive the flip-flop memory cell, providing SET, RESET, CLOCK and DATA inputs.

The purpose of the module is to allow the combination of various gate events and CVs to generate responses, rhythms, etc.

When the SET comparator output is HIGH, it will set the Q output (K) of the first Memory cell HIGH.

When the RESET comparator output is HIGH, it will set the Q(inv) output (L) of the first Memory cell HIGH.

Note that when both the SET and RESET comparator outputs are HIGH, both the Q and Q(inv) outputs of the first memory cell will be HIGH. When the inputs change, the memory cell will take on the state of the last of the two inputs to fall LOW.

The memory cell can also be programmed with a two-step procedure. The output state of the DATA comparator will be clocked into the first memory cell when the output of the CLOCK comparator goes from LOW to HIGH. At the same time, the previous state of the first memory cell will be loaded into the second memory cell, the result being available at outputs M and N.

A little on how it works:

The schematic for Quad Comparator and Memory Cell module.