This module is a very standard logarithmic response ADSR envelope generator. It is not voltage controlled. It is for use where a basic envelope generator is adequate. There are two identical envelope generators on the PCB.

How to use this module:

Connect your external GATE signal to the Gate input. Adjust the pots as required. Rotating the pots clockwise will increase the time of any particular stage, or in the case of SUSTAIN increase voltage of the sustain portion of the cycle. The output is exponential due to the basic resistor/capacitor configuration used in the timing cycle.

• A push button is supplied to provide a manual GATE signal.
• Upon the GATE input going HIGH the UEG immediately begins it's ATTACK cycle. This will continue until one of the following occurs:
  • the GATE input returns to LOW. If this occurs, the UEG immediately goes into its RELEASE cycle, the output decreasing to zero. Thus with longer attack times set, a short GATE signal will produce an envelope with a reduced output, which can be useful for expression.
  • the attack peak is reached (approximately 5 volts). When this occurs, the UEG immediately goes into its DECAY cycle, where the output will decrease until it reaches the voltage set by the SUSTAIN pot. If this is zero, the output will drop to zero, effectively terminating the cycle. If it is above zero, this voltage will be held as long as the GATE input is HIGH. When the GATE input returns to LOW, the UEG immediately goes into its RELEASE cycle, the output decreasing to zero.
• The retrigger input (RETRIG) restarts the ATTACK portion of the cycle if the GATE input is HIGH. It can be used to modulate the ATTACK, DECAY, SUSTAIN portion of the cycle. A rapid burst of pulses on this input can push the envelope higher than the usual peak if the ATTACK is set to a sufficiently short length.
• The LED and ATTACK PULSE output are active during the ATTACK part of the cycle. This allows the UEG to be used as a gate to pulse converter, the pulse length controlled by the setting of the ATTACK pot.
• The UEG CANNOT be set to self oscillate or cycle.

A little on how it works:

The schematic of the Utility Envelope Generator.

IC1A is the GATE detector and is set to detect signals over about 2 volts. It's output falls when a gate signal is present. This turns off the RELEASE circuit and trips the ATTACK/DECAY bistable IC1D. This "bistable" is actually a schmitt trigger that also servers as the peak detector for the ATTACK period.

IC1C is the output buffer. It follows the voltage on the main timing capacitor C. Its signal is fed back into IC1D. When the ATTACK peak voltage is reached (approximately 5V when running from +/-15V power rails) the bistable resets, shutting off the ATTACK circuit and turning on the DECAY circuit.

The DECAY circuit discharges capacitor C until it reaches the voltage set by the SUSTAIN pot.

When the GATE input goes LOW the bistable is set, if it hasn't already been set by other circuit elements, ready for the next ATTACk cycle, and the RELEASE circuit is turned on, and discharges capacitor C.