The CD4006B 18-stage static shift register is comprised of four separate shift register sections, two sections of four stages and two sections of five stages. Each section has an independent data input. Outputs are available at the fourth stage and the fifth stage of each section. A common clock signal is used for all stages. Data is shifted to the next stage on the negative-going transition of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8, and 9 stages, or single register sections of 10, 12, 13, 14, 16, 17, and 18 stages can be implemented using one package.
-Wide supply voltage range 3.0V to 15V
-High noise immunity 0.45 VDD (typ.)
-Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS
-Low clock input capacitance 6 pF (typ.)
-Medium speed 10 MHz (typ.) (with VDD e 10V)
-Fully static operation
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