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CGS62 - Slope Detector | Cat Girl Synth

CGS62 - Slope Detector | Cat Girl Synth


The slope detector is an event-driven gate/trigger generating device. It monitors a control voltage, and responds according to what that voltage is doing.

This is a PCB only suitable for multiple formats

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The slope detector is an event-driven gate/trigger generating device. It monitors a control voltage, and responds according to what that voltage is doing. If the voltage is rising, the slope detector gives a "gate" output (approx. 5V) on its "rising" output. Likewise, if the voltage is falling, the slope detector gives an output on its "falling" output. The duration of this gate signal depends on the incoming CV and the setting of the sensitivity pot. When the CV is remaining constant, the "steady" output activates.

These gate signals can be used to fire envelope generators dependent on the action of the CV, for example opening a filter when a melody is rising in pitch, and closing it when the melody is falling in pitch. It can also be used to generate gate signals from LFOs, envelope generators, to advance sequencers etc.

The sensitivity pot allows the slope detector to work with either relatively fast events, like the edges of a square wave pulse train, or very slow events, such as the sine output of an LFO being used to drive filter/phaser sweeps.


A little on how it works:


Slope Detector

The schematic for the slope detector.


The circuit can be divided into three parts, "rising", "falling" and "steady". Both the rising and falling circuits are identical with the exception of the polarity of their detectors.

Consider the falling part of the circuit - the upper op-amp (used as a comparator) and its associated components. At rest, the voltage differences between pin 5 and 6 of the op-amp will be very close. The 100n capacitor will have charged or discharged through the sensitivity resistor/pot until the voltage across it equals that at the input. Thus the voltage at the inverting input of the op-amp (pin 6) will be equal to the voltage at the cv input. The voltage at the non-inverting input of the op-amp (pin 5) will be slightly higher, pulled up by the 1M/2k2 voltage divider, just enough to keep the comparator output high. The reason why a high is needed here (the opposite of what we really want) is because the next stage is a PNP inverting buffer. When the comparator output is high, the PNP will be switched off, allowing the 1k resistor between the output jack and earth to pull the output to 0V (LOW).

If the input voltage begins to fall, the voltage at pin 5 will immediately follow it, albeit slightly higher in value. The voltage on pin 6, however, is initially held where it was by the 100n capacitor, and slowly charges or discharges through the sensitivity pot/resistor. Thus while the input voltage is falling, the voltage at pin 5 will be lower than that at pin 6, causing the output of the comparator to fall, switching on the PNP inverter, pulling the output jack high via the 1k8 resistor. The 1k8/1k output divider reduces the output voltage to around 5.3 volts. The transistor also switches on the LED at the same time.

If the input voltage becomes steady, the 100n capacitor will eventually charge/discharge to the same voltage as the input voltage, and the voltage on pin 5 of the op-amp will again be slightly higher than that on pin 6 of the op-amp, so the output of the op-amp will swing high, switching off the transistor.

A rising voltage at the input will merely lift the voltage at pin 5 even higher than the delayed voltage at pin 6, thus ensuring the op-amp output remains high, and the buffer output in its OFF state.

The lower section of the circuit based around the second op-amp works in exactly the same way, but inverted so that it detects rising voltages.

When the input voltage is changing, either one or the other of the outputs of the comparators will be HIGH (near the positive supply voltage) while the other is LOW (near the negative supply voltage). The two 100k resistors between them function as a voltage divider, the voltage at their junction being near enough to 0 volts. This is not enough to turn on the NPN transistor. However, when the input voltage is steady, the outputs of both comparators will be high, and the two 100k resistors will no longer function as a voltage divider, but will instead behave as if they were in parallel, connected to the positive supply rail (less the internal op-amp voltage drop), turning on the NPN transistor. This will turn on the following PNP buffer, giving a HIGH at the "steady" output.

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